Rapid advances in AI have made advanced semiconductors critical to scientific progress, economic growth, and national security. Yet the complexity of chip manufacturing and the concentration of its supply chain make hardware integrity difficult to verify. This paper surveys the core challenges and techniques for verifiable semiconductor fabrication. We develop a threat model spanning design through manufacturing that highlights high-impact attack vectors. Evaluating existing countermeasures shows that no single technique provides sufficient protection. Accordingly, we argue that a defense-in-depth architecture with tiered assurances is required, where assurance is tiered by chip criticality, prioritizing the products and workflows in which successful attacks would be most consequential. Neutral third-party verification authorities and privacy-preserving data-sharing mechanisms can help overcome industry opacity. Ultimately, this study aims to create shared technical foundations that make hardware trust measurable rather than assumed. By establishing shared, auditable verification mechanisms that can operate across jurisdictions, this work aims to enable international cooperation on AI governance, even among geopolitical competitors.
